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USB2601/USB2602
4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub
PRODUCT FEATURES
Hub Controller Provides Three USB2.0 Downstream Ports via internal USB2.0 Hub
-- Multi Transaction Translator for FS/LS devices attached
Datasheet
-- 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM -- Double Buffered Bulk Endpoint -- Bi-directional 512 Byte Buffer for Bulk Endpoint -- 64 Byte RX Control Endpoint Buffer -- 64 Byte TX Control Endpoint Buffer
Flash Media Controller Complete System Solution for interfacing SmartMediaTM (SM) or xD Picture CardTM (xD)1, Memory StickTM (MS), High Speed Memory Stick (HSMS), Memory Stick PRO (MSPRO), MS DuoTM, Secure Digital (SD), Mini-Secure Digital (Mini-SD), TransFlash (SD), MultiMediaCardTM (MMC), Reduced Size MultiMediaCard (RS-MMC), NAND Flash, Compact FlashTM (CF) and CF UltraTM I & II, and CF form-factor ATA hard drives to USB2.0 bus
-- Supports USB Bulk Only Mass Storage Compliant Bootable BIOS
Internal Program Memory Interface
-- 64K Byte Internal Code Space
Support for simultaneous operation of all above devices. (only one at a time of each of the following groups supported: CF or ATA drive, SM or XD or NAND, SD or MMC) On-Chip 4-Bit High Speed Memory Stick and MS PRO Hardware Circuitry On-Chip firmware reads and writes High Speed Memory Stick and MS PRO 1-bit ECC correction performed in hardware for maximum efficiency Hardware support for SD Security Command Extensions 3.3 Volt I/O with 5V input tolerance on VBUS, Port Power and Over-Current Sense pins On-chip power FETs for supplying flash media card power with minimum board components 8051 8 bit microprocessor
-- Provides low speed control functions -- 30 Mhz execution speed at 4 cycles per instruction average -- 12K Bytes of internal SRAM for general purpose scratchpad
On Board 24Mhz Crystal Driver Circuit Can be clocked by an external 24MHz source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock 11 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.
-- Inputs capable of generating interrupts with either edge sensitivity
Configuration of Hub and Flash Media features controlled either by internal defaults or via single external EEPROM. User configurable features:
-- -- -- -- -- -- -- -- -- Full or Partial Card compliance checking LUN configuration and assignment Write Protect Polarity Cover Switch operation for xD compliance Inquiry Command operation SD Write Protect operation Older CF card support Force USB 1.1 reporting Internal or External Power FET operation
Compatible with Microsoft WinXP, WinME, Win2K SP3&4, Apple OS10 and Linux Multi-LUN Mass Storage Class Drivers Win2K, Win98/98SE and Apple OS8.6 and OS9 Multi-LUN Mass Storage Class Drivers are available from SMSC 128 Pin TQFP Package (1.0mm height, 14mm x14mm footprint); green, lead-free package also available
1.xD Picture Card not applicable to USB2601
SMSC USB2601/USB2602
DATASHEET
Revision 1.5 (07-24-06)
4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
ORDER NUMBER(S): USB2601/USB2602-NE-XX FOR 128 PIN, TQFP PACKAGE USB2601/USB2602-NU-XX FOR 128 PIN, TQFP PACKAGE (GREEN, LEAD-FREE)
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 High-Speed Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Media Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 128-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 128-Pin List Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 6.2 PIN Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 7.2 7.3 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 9 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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List of Figures
Figure 4.1 USB2601/USB2602 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.1 USB2601/USB2602 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8.1 USB2601/USB2602 128-Pin TQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of Tables
Table 3.1 Table 3.2 Table 6.1 Table 8.1 Table 9.1 USB2601/USB2602 128-Pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 USB2601/USB2602 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB2601/USB2602 Buffer Type Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USB2601/USB2602 128-Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 GPIO Usage (ROM Rev -01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Chapter 1 General Description
The USB2601/USB2602 is an Integrated "combo" High-Speed USB hub and Flash Media Controller. The Flash media controller permanently resides on Port 1 of the Integrated USB hub.
1.1
High-Speed Hub
The integrated SMSC Hub is fully compliant with the USB2.0 Specification and will attach to a USB host as a Full-Speed Hub or as a Full-/High-Speed Hub. The Hub supports Low-Speed, Full-Speed, and High-Speed (if operating as a High-Speed Hub) downstream devices on all of the enabled downstream ports. A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture ensures maximum USB throughput for each connected device when operating with mixed-speed peripherals. The Hub works with an external USB power distribution switch device to control VBUS switching to downstream ports, and to limit current and sense over-current conditions. All required resistors on the USB ports are integrated into the Hub. This includes all series termination resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. Throughout this document the upstream facing port of the hub will be referred to as the upstream port, and the downstream facing ports will be called the downstream ports. Three externally available ports are available for general USB device connectivity.
1.2
Flash Media Controller
The Bulk Only Mass Storage Class Peripheral Controller intended for supporting CompactFlash (CF and CF Ultra I/II) in True IDE Mode only, SmartMedia (SM) and XD cards, Memory Stick (MS), Memory Stick DUO (MSDUO) and Memory Stick Pro (MSPRO), Secure Digital (SD), and MultiMediaCard (MMC) flash memory devices. It provides a single chip solution for the most popular flash memory cards in the market. The device consists of buffers, Fast 8051 microprocessor with expanded scratchpad, and program SRAM, and CF, MS, SM and SD controllers. The SD controller supports both SD and MMC devices. SM controller supports both SM and xD cards. 12K bytes of scratchpad SRAM and 768 Bytes of program SRAM are also provided. Eleven GPIO pins are provided for indicators, external serial EEPROM for OEM ID and system configuration information, and other special functions. Internal power FETs are provided to directly supply power to the xD/SM, MMC/SD and MS/MSPro cards. The internal ROM program is capable of implementing any combination of single or multi-LUN CF/SD/MMC/SM/MS reader functions with individual card power control and activity indication. SMSC also provides licenses** for Win98 and Win2K drivers and setup utilities. Note: Please check with SMSC for precise features and capabilities for the current ROM code release.
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or
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with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
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Chapter 2 Acronyms
SM: SmartMedia SMC: SmartMedia Controller FM: Flash Media FMC: Flash Media Controller CF: Compact Flash CFC: CompactFlash Controller SD: Secure Digital SDC: Secure Digital Controller MMC: MultiMediaCard MS: Memory Stick MSC: Memory Stick Controller TPC: Transport Protocol Code. ECC: Error Checking and Correcting CRC: Cyclic Redundancy Checking
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Chapter 3 Pin Table
3.1 128-Pin Package
Table 3.1 USB2601/USB2602 128-Pin Package
UPSTREAM USB2.0 INTERFACE (3 PINS) USBUP_DP USBUP_DM VBUS_DET
3-PORT USB2.0 INTERFACE (16 PINS) USBDN_DP2 USBDN_DP4 PRTPWR4 GR2_N USBDN_DM2 USBDN_DM4 OCS2_N GR3_N USBDN_DP3 PRTPWR2 OCS3_N GR4_N USBDN_DM3 PRTPWR3 OCS4_N PRTPWR_POL
CompactFlashINTERFACE (28 Pins) CF_D0 CF_D4 CF_D8 CF_D12 CF_nIOR CF_IORDY CF_SA1 CF_D1 CF_D5 CF_D9 CF_D13 CF_nIOW CF_nCS0 CF_SA2 CF_D2 CF_D6 CF_D10 CF_D14 CF_IRQ CF_nCS1 CF_nCD1 CF_D3 CF_D7 CF_D11 CF_D15 CF_nRESET CF_SA0 CF_nCD2
SmartMedia INTERFACE (17 Pins) SM_D0 SM_D4 SM_ALE SM_nWP SM_nWPS Memory Stick INTERFACE (7 Pins) MS_BS MS_D1 MS_SDIO/MS_D0 MS_D2 SD INTERFACE (7 Pins) SD_CMD SD_DAT2 SD_CLK SD_DAT3 SD_DAT0 SD_nWP SD_DAT1 MS_SCLK MS_D3 MS_INS SM_D1 SM_D5 SM_CLE SM_nB/R SM_D2 SM_D6 SM_nRE SM_nCE SM_D3 SM_D7 SM_nWE SM_nCD
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Table 3.1 USB2601/USB2602 128-Pin Package (continued)
MISC (23 Pins) GPIO1 GPIO6 GPIO10/CRD_PWR1 GPIO14 ATEST CLK_SEL0 GPIO2 GPIO7 GPIO11/CRD_PWR2 GPIO15 RBIAS CLK_SEL1 GPIO4 GPIO8/CRD_PWR0 GPIO12 TEST XTAL1/CLKIN SEL_CLKDRV GPIO5 GPIO9 GPIO13 RESET_N XTAL2
ANALOG POWER (5 Pins) (3)VDDA33 VDD33PLL VDD18PLL
DIGITAL, POWER & GROUND (22 Pins) (5)VDD33 (11)VSS Total 128 (3)VDD18 (3)NC
3.2
128-Pin List Table
Table 3.2 USB2601/USB2602 128-Pin TQFP
PIN # 1 2 3 4 5 6
NAME PRTPWR _POL PRTPWR 2 OCS2_N PRTPWR 3 OCS3_N PRTPWR 4 OCS4_N VDDA33 USBDN_ DP3 USBDN_ DM3 VSS USBDN_ DM4
MA 12 12 12
PIN # 33 34 35 36 37 38
NAME VDD18 VSS VSS SM_nWPS SM_CLE SM_nCE
MA 8 8
PIN # 65 66 67 68 69 70
NAME CF_D7 CF_D15 CF_nCS0 CF_nCS1 CF_nIOR CF_nIOW
MA 8 8 8 8 8 8
PIN # 97 98 99 100 101 102
NAME SD_nWP SD_DAT1 SD_DAT0 SD_CLK VDD33 GPIO11/ CRD_PWR 2 SD_CMD SD_DAT3 SD_DAT2 GPIO4 GPIO5 VSS
MA 8 8 8 -
7 8 9 10 11 12
--
39 40 41 42 43 44
SM_ALE SM_nRE SM_nWE SM_nB/R VDD33 GPIO10/ CRD_PWR1
8 8 8 -
71 72 73 74 75 76
CF_IRQ CF_nRESET CF_IORDY CF_SA2 CF_SA1 CF_SA0
8 8 8 8 8 8
103 104 105 106 107 108
8 8 8 8 8 -
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Table 3.2 USB2601/USB2602 128-Pin TQFP (continued)
PIN # 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME USBDN_ DP4 VDDA33 VDD33 GR2_N GR3_N GR4_N GPIO6 MS_BS MS_D1 MS_SDIO /MS_D0 MS_D2 MS_INS MS_D3 MS_ SCLK SEL_CLK DRV CLK_SEL 1 CLK_SEL 0 NC NC NC Notes: RBIAS is connected to the Analog Ground plane VSS via a resistor. When the internal 1.8V regulators are enabled, VDD18 (Pin 86) & VDD18PLL (Pin 124), MUST have a 10uf +/- 20%, (equivalent series resistance (ESR) <0.1ohm) bypass capacitor to VSS. These capacitors must be as close to the pins as possible. MA 8 8 8 8 8 8 8 8 8 8 PIN # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME SM_nWP SM_D0 SM_D1 SM_D7 SM_D2 SM_D6 SM_D3 SM_D5 SM_D4 SM_nCD GPIO9 CF_nCD1 CF_D3 CF_D11 CF_D4 CF_D12 CF_D5 CF_D13 CF_D6 CF_D14 MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME CF_D0 CF_D1 CF_D8 CF_D2 CF_D9 CF_D10 CF_nCD2 VSS VSS VDD18 VDD33 GPIO1 GPIO2 GPIO7 VDD33 GPIO8/ CRD_PWR0 GPIO12 GPIO13 GPIO14 GPIO15 MA 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME VSS USBUP_D M USBUP_D P VDDA33 USBDN_D P2 USBDN_D M2 VSS VBUS_ DET VSS RESET_N VDD18 TEST VSS XTAL2 XTAL1/ CLKIN VDD18PLL VDD33PLL ATEST RBIAS VSS MA 12 -
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Chapter 4 Pin Configuration
Figure 4.1 USB2601/USB2602 128-Pin TQFP
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Chapter 5 Block Diagram
Figure 5.1 USB2601/USB2602 Block Diagram
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Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "n" or "_N"symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "n" is not present before the signal name (or "_N" after the signal name), the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
6.1
PIN Descriptions
NAME SYMBOL BUFFER TYPE UPSTREAM USB INTERFACE DESCRIPTION
USB Bus Data Detect Upstream VBUS Power
USBUP_DM USBUP_DP VBUS_DET
IO-U I/O12
These pins connect to the Upstream USB bus data signals. Detects state of Upstream VBUS power. The SMSC Hub monitors VBUS_DET to determine when to assert the internal D+ pull-up resistor (signalling a connect event). When designing a detachable hub, this pin must be connected to the VBUS power pin of the USB port that is upstream of the hub. For self-powered applications with a permanently attached host, this pin must be pulled-up to either 3.3V or 5.0V (typically VDD33).
3-PORT USB INTERFACE USB Bus Data USBDN_DM [4:2} USBDN_DP [4:2} PRTPWR[4:2] IO-U These pins connect to the Downstream USB bus data signals.
USB Power Enable
I/O12
Enables power to USB peripheral devices (downstream). The active signal level of the PRTPWR[4:2] pins is determined by the Power Polarity Strapping function of the PRTPWR_POL pin.
Port Power Polarity Strapping
PRTPWR_POL
I/O12
Port Power Polarity strapping determination for the active signal polarity of the PRTPWR[4:2] pins. While RESET_N is asserted, the logic state of this pin will (though the use of internal combinatorial logic) determine the active state of the PRTPWR[4:2] pins in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. `1' = PRTPWR[4:2] pins have an active `high' polarity `0' = PRTPWR[4:2] pins have an active `low' polarity
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NAME Over Current Sense
SYMBOL OCS[4:2]_N
BUFFER TYPE IPU
DESCRIPTION Input from external current monitor indicating an overcurrent condition. {Note: Contains internal pull-up to 3.3V supply} Green indicator LED for ports 2, 3 and 4. Will be active low when LED support is enabled via EEPROM or SMBus.
Green LED
GR[4:2]_N
I/O8
CompactFlash (In True IDE mode) INTERFACE CF Chip Select 1 CF Chip Select 0 CF Register Address 2 CF Register Address 1 CF Register Address 0 CF Interrupt CF Data 15-8 CF_nCS1 CF_nCS0 CF_SA2 CF_SA1 CF_SA0 CF_IRQ CF_D[15:8] O8PU O8PU O8 O8 O8 IPD I/O8PD This pin is the active low chip select 1 signal for the CF ATA device This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. This pin is the register select address bit 2 for the CF ATA device. This pin is the register select address bit 1 for the CF ATA device This pin is the register select address bit 0 for the CF ATA device. This is the active high interrupt request signal from the CF device. The bi-directional data signals CF_D15-CF_D8 in True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pulldown resistor. CF Data7-0 CF_D[7:0] I/O8PD The bi-directional data signals CF_D7-CF_D0 in the True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pulldown resistor. IO Ready CF_IORDY IPU This pin is active high input signal. This pin has an internally controlled weak pull-up resistor. CF Card Detection2 CF_nCD2 IPU This card detection pin is connected to the ground on the CF device, when the CF device is inserted. This pin has an internally controlled weak pull-up resistor. CF Card Detection1 CF_nCD1 IPU This card detection pin is connected to ground on the CF device, when the CF device is inserted. This pin has an internally controlled weak pull-up resistor. CF Hardware Reset CF_nRESET O8 This pin is an active low hardware reset signal to CF device.
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NAME CF IO Read CF IO Write Strobe
SYMBOL CF_nIOR CF_nIOW
BUFFER TYPE O8 O8
DESCRIPTION This pin is an active low read strobe signal for CF device. This pin is an active low write strobe signal for CF device.
SmartMedia INTERFACE SM Write Protect SM_nWP O8PD This pin is an active low write protect signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Address Strobe SM_ALE O8PD This pin is an active high Address Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Command Strobe SM_CLE O8PD This pin is an active high Command Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Data7-0 SM_D[7:0] I/O8PD These pins are the bi-directional data signal SM_D7SM_D0. The bi-directional data signal has an internal weak pulldown resistor. SM Read Enable SM_nRE 08PU This pin is an active low read strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET. 08 If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply). This pin is an active low write strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET. 08 If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply). A write-protect seal is detected, when this pin is low. This pin has an internally controlled weak pull-up resistor. SM_nB/R I This pin is connected to the BSY/RDY pin of the SM device. An external pull-up resistor is required on this signal. The pull-up resistor must be pulled up to the same power source that powers the SM/NAND flash device.
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SM Write Enable
SM_nWE
O8PU
SM Write Protect Switch
SM_nWPS
IPU
SM Busy or Data Ready
DATASHEET
4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
NAME SM Chip Enable
SYMBOL SM_nCE
BUFFER TYPE O8PU
DESCRIPTION This pin is the active low chip enable signal to the SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET.
08
If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply). This is the card detection signal from SM device to indicate if the device is inserted. This pin has an internally controlled weak pull-up resistor.
SM Card Detection
SM_nCD
IPU
MEMORY STICK INTERFACE MS Bus State MS_BS O8 This pin is connected to the BS pin of the MS device. It is used to control the Bus States 0, 1, 2 and 3 (BS0, BS1, BS2 and BS3) of the MS device. MS_SDIO/MS_ D0 I/O8PD This pin is a bi-directional data signal for the MS device. Most significant bit (MSB) of each byte is transmitted first by either MSC or MS device. The bi-directional data signal has an internal weak pulldown resistor. MS System Data In/Out MS_D1 I/O8PD This pin is a bi-directional data signal for the MS device. This pin has internally controlled weak pull-up and pulldown resistors for various operational modes. MS_D[3:2] I/O8PD This pin is a bi-directional data signal for the MS device. The bi-directional data signal has an internal weak pulldown resistor. MS_INS IPU This pin is the card detection signal from the MS device to indicate, if the device is inserted. This pin has an internally controlled weak pull-up resistor. MS System CLK MS_SCLK O8 This pin is an output clock signal to the MS device. The clock frequency is software configurable. SD INTERFACE SD Data3-0 SD_DAT[3:0] I/O8PU These are bi-directional data signals. These pins have internally controlled weak pull-up resistors. SD_CLK O8 This is an output clock signal to SD/MMC device. The clock frequency is software configurable.
MS System Data In/Out
MS System Data In/Out MS Card Insertion
SD Clock
SMSC USB2601/USB2602
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NAME SD Command
SYMBOL SD_CMD
BUFFER TYPE I/O8PU
DESCRIPTION This is a bi-directional signal that connects to the CMD signal of SD/MMC device. This pin has an internally controlled weak pull-up resistor.
SD Write Protected
SD_nWP
IPD
This pin is an input signal with an internal weak pulldown. This pin has an internally controlled weak pull-down resistor. MISC
General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O GPIO6
GPIO1 GPIO2 GPIO4 GPIO5 GPIO6
I/O8 I/O8 I/O8 I/O8 IPU
This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin has an internal weak pull-up resistor that is enabled or disabled by the state of RESET_N. The pull-up is enabled when RESET_N is active. The pull-up is disabled, when the RESET_N is inactive (some clock cycles later, after the rising edge of RESET_N). The state of this pin is latched internally on the rising edge of RESET_N to determine if internal or external program memory is used. The state latched is stored in ROMEN bit of GPIO_IN1 register.
I/O8
After the rising edge of RESET_N, this pin may be used as GPIO6. When this pin is left unconnected or pulled high by a weak pull-up resistor, the USB2601/USB2602 uses the internal ROM for program execution. This pin may be used either as input, edge sensitive interrupt input, or output.
General Purpose I/O General Purpose I/O Or Card Power General Purpose I/O General Purpose I/O Or Card Power
GPIO7 GPIO8/ CRD_PWR0
I/O8 I/O8
This pin may be used either as input, edge sensitive interrupt input, or output. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 100mA.
GPIO9 GPIO10/ CRD_PWR1
I/O8 I/O8
This pin may be used either as input, edge sensitive interrupt input, or output. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 100mA.
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SMSC USB2601/USB2602
4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
NAME General Purpose I/O Or Card Power General Purpose I/O RESET input TEST Input USB Transceiver Bias Analog Test
SYMBOL GPIO11/ CRD_PWR2
BUFFER TYPE I/O8
DESCRIPTION GPIO: These pins may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 200mA.
GPIO[15:12] RESET_N TEST RBIAS
I/O8 IS IPD I
These pins may be used either as input, or output. This active low signal is used by the system to reset the chip. The active low pulse should be at least 1s wide. Used for testing the IC. User must treat either as a noconnect, or connect to the ground. A 12.0k, 1.0% resistor is attached from VSS to this pin, in order to set the transceiver's internal bias currents. This signal is used for testing the analog section of the chip and should be connected to VDDA33 for normal operation. 24Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 24Mhz clock when a crystal is not used. Note: The `SEL_CLKDRV and CLK_SEL[1:0]' pins will be sampled while RESET_N is asserted, and the value will be latched upon RESET_N negation. This will determine the clock source and value.
ATEST
AIO
Crystal Input/External Clock Input
XTAL1/ CLKIN
ICLKx
Crystal Output
XTAL2
OCLKx
24Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. SEL_CLKDRV. During RESET_N assertion, this pin will select the operating clock mode (crystal or externally driven clock source), and a weak pull-down resistor is enabled. When RESET_N is negated, the value will be internally latched and the internal pull-down will be disabled. `0' = Crystal operation (24MHz) `1' = Externally driven clock source (24MHz)
Select Clock Drive
SEL_CLKDRV
I/O8PD
Clock Select
CLK_SEL[1:0]
I/O8PD
SEL[1:0]. During RESET_N assertion, these pins will select the operating frequency of the external clock, and the corresponding weak pull-down resistors are enabled. When RESET_N is negated, the value on these pins will be internal latched and the internal pulldowns will be disabled. SEL[1:0] SEL[1:0] SEL[1:0] SEL[1:0] = = = = `00'. 24MHz `01'. RESERVED `10'. RESERVED `11'. RESERVED
ANALOG POWER 1.8V PLL Power 3.3V PLL Power
SMSC USB2601/USB2602
VDD18PLL VDD33PLL
1.8v Output from the internal 1.8V PLL regulator 3.3V Input to the internal 1.8V PLL regulator.
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DATASHEET
4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
NAME 3.3V Analog Power
SYMBOL VDDA33
BUFFER TYPE
DESCRIPTION 3.3v Analog PHY Power
DIGITAL POWER, GROUNDS, and NO CONNECTS 1.8v Digital Core Power VDD18 +1.8V Core power All VDD18 pins must be connected together on the circuit board. VDD33 3.3V Power & Regulator Input. pin 87 supplies 3.3V power to the internal 1.8V VDD18 regulator. VSS NC Ground Reference No Connect. No trace or signal should be routed/attached to these pins.
3.3v Power & & Voltage Regulator Input Ground No Connect
Notes: Hot-insertion capable card connectors are required for all flash media. It is required for SD connector to have Write Protect switch. This allows the chip to detect MMC card. nMCE is normally asserted except when the 8051 is in standby mode.
6.2
Buffer Type Descriptions
Table 6.1 USB2601/USB2602 Buffer Type Descriptions
BUFFER I IPU IPD IS I/O8 I/O8PU I/O8PD I/O12 O8 O8PU O8PD ICLKx OCLKx I/O-U AIO Input Input with internal weak pull-up resistor. Input with internal weak pull-down resistor. Input with Schmitt trigger Input/Output buffer with 8mA sink and 8mA source. Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor. Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-down resistor. Input/Output, 12mA Output buffer with 8mA sink and 8mA source. Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor. Output buffer with 8mA sink and 8mA source, with an internal weak pull-down resistor. XTAL clock input XTAL clock output Analog Input/Output Defined in USB specification Analog Input/Output DESCRIPTION
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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
Chapter 7 DC Parameters
7.1 Maximum Guaranteed Ratings
Operating Temperature Range ............................................................................................0oC to +70oC Storage Temperature Range............................................................................................. -55o to +150oC Lead Temperature Range (soldering, 10 seconds) ...................................................................... +325oC Positive Voltage on GPIO3, with respect to Ground......................................................................... 5.5V Positive Voltage on any signal pin, with respect to Ground ............................................................. 4.6V Positive Voltage on XTAL1, with respect to Ground ......................................................................... 4.0V Positive Voltage on XTAL2, with respect to Ground ......................................................................... 2.5V Negative Voltage on GPIO8, 10 & 11, with respect to Ground (see Note 7.2)............................... -0.5V Negative Voltage on any pin, with respect to Ground ..................................................................... -0.5V Maximum VDD18, VDD18PLL .............................................................................................................. +2.5V Maximum VDD33, VDDA33 ................................................................................................................. +4.6V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 7.1 When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. When internal power FET operation of these pins is enabled, these pins may be simultaneously shorted to ground or any voltage up to 3.63V indefinitely, without damage to the device as long as VDD33 and VDDA33 are less than 3.63V and TA is less than 70C.
Note 7.2
7.2
DC Electrical Characteristics
(TA = 0C - 70C, VDD33, VDDA33 = +3.3 V 0.3 V, VDD18, VDD18PLL = +1.8 V 10%,) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I,IPU & IPD Type Input Buffer Low Input Level High Input Level Pull Down Pull Up VILI VIHI PD PU 2.0 72 58 0.8 V V A A TTL Levels
SMSC USB2601/USB2602
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PARAMETER IS Type Input Buffer Low Input Level High Input Level Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8. O8PU & 08PD Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILI VIHI VHYSI 2.0 500
0.8
V V mV
TTL Levels
VILCK VIHCK 2.2
0.4
V V
IIL IIH
-10 -10
+10 +10
A mA
VIN = 0 VIN = VDD33
VOL
0.4
V
IOL = 8 mA @ VDD33= 3.3V IOH = -8mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.3)
High Output Level
VOH
VDD33 - 0.4
V
Output Leakage
IOL PD
-10
+10
A A A
Pull Down
72
Pull Up I/O8, I/O8PU & I/O8PD Type Buffer Low Output Level
PU
58
VOL
0.4
V
IOL = 8 mA @ VDD33= 3.3V IOH = -8 mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.3)
High Output Level
VOH
VDD33 -0.4
V
Output Leakage
IOL PD
-10
+10
A
Pull Down
72
A
Pull Up
PU
58
A
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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
PARAMETER I/O12 Type Buffer Low Output Level High Output Level Output Leakage
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL VOH IOL 2.4
0.4
V V
IOL = 12mA @ VDD33 = 3.3V IOH = -4mA @ VDD33 = 3.3V VIN = 0 to VDD33 (Note 1)
+10
uA
IO-U (Note 7.4) Integrated Power FET for GPIO8 & GPIO10 Output Current IOUT ISC RDSON tDSON 100 mA GPIO8, or 10; VdropFET = 0.23V GPIO8, or 10; VoutFET = 0V GPIO8, or 10; IFET = 70mA GPIO8, or 10; CLOAD = 10F
Short Circuit Current Limit
140
mA s
On Resistance
2.1
Output Voltage Rise Time Integrated Power FET for GPIO11 Output Current
800
IOUT ISC RDSON tDSON
200
mA
GPIO11; VdropFET = 0.46V GPIO11; VoutFET = 0V GPIO11; IFET = 70mA GPIO11; CLOAD = 10F
Short Circuit Current Limit
181
mA s
On Resistance
2.1
Output Voltage Rise Time
800
Supply Current Hub, Card Reader, Unconfigured High-Speed Host Full-Speed Host Supply Current Configured (High-Speed Host) 3 Ext Ports @HS Card Reader Active
302 mA ICCINIT ICCINIT 90 83 mA mA
Total from all supplies
SMSC USB2601/USB2602
DATASHEET
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PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Supply Current Configured (High-Speed Host) 1 Ext Port @HS Card Reader Active Supply Current Configured (Full-Speed Host) 1 Ext Port @ FS/LS Card Reader Active Supply Current Suspend Supply Current Reset
Note 7.3 Note 7.4 Note 7.5 Note 7.6 ICSBY IRST 200 298 91 mA A A 242 mA
Total from all supplies
Total from all supplies
Total from all supplies. Total from all supplies.
Output leakage is measured with the current pins in high impedance. See Appendix A for USB DC electrical characteristics. The Maximum power dissipation parameters of the package should not be exceeded The assignment of each Integrated Card Power FET to a designated Card Connector is controlled by both firmware and the specific board implementation. Firmware will default to the settings listed in Table 9.1, "GPIO Usage (ROM Rev -01)," on page 26
7.3
Capacitance
TA = 25C; fc = 1MHz; VDD18, VDD18PLL = 1.8V LIMITS PARAMETER SYMBOL CIN MIN TYP MAX 20 UNIT pF TEST CONDITION All pins except USB pins (and pins under test tied to AC ground)
Clock Input Capacitance
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
Chapter 8 Package Outline
Figure 8.1 USB2601/USB2602 128-Pin TQFP Package Outline Table 8.1 USB2601/USB2602 128-Pin TQFP Package Parameters
MIN A A1 A2 D D1 E E1 H L L1 e q W R1 R2 ccc 0o 0.13 0.08 0.08 ~ Notes:
1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is 0.035 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. 3. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated.
NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.40 Basic ~ 0.18 ~ ~ ~
MAX 1.20 0.15 1.05 16.20 14.20 16.20 14.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 0.08
REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
~ 0.05 0.95 15.80 13.80 15.80 13.80 0.09 0.45 ~
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DATASHEET
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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs and HS Hub Datasheet
Chapter 9 GPIO Usage
Table 9.1 GPIO Usage (ROM Rev -01)
NAME GPIO1 ACTIVE LEVEL H SYMBOL Flash Media Activity LED/ xD_Door DESCRIPTION AND NOTE Indicates media activity. Media or USB cable must not be removed with LED lit. Also may be used for xD Door functionality Serial EE PROM chip select USB V bus detect Serial EE PROM input/output and xD Identify HS Indicator LED or SD Card Detect Switch input A16 address line connect for DFU or debug LED indicator optional. Serial EE PROM clock output or Unconfigured LED. Memory Stick Card Power Control, or Internal Power FET0. CompactFlash Card Power Control SmartMedia Card Power Control, or Internal Power FET1. SD/MMC Card Power Control, or Internal Power FET2. Memory Stick Activity Indicator, or Media Activity LED. CompactFlash Activity Indicator SmartMedia Activity Indicator SD/MMC Activity Indicator
GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15
H H H H H H L L L L H H H H
EE_CS V_BUS EE_DIN/EE_DOUT/xDID HS_IND/SD_CD A16/ROMEN EE_CLK/ UNCONF_LED MS_PWR_CTRL/ CRD_PWR0 CF_PWR_CTRL SM_PWR_CTRL/ CRD_PWR1 SD/MMC_PWR_CTRL/ CRD_PWR2 MS_ACT_IND/ Media Activity CF_ACT_IND SM_ACT_IND SD/MMC_ACT_IND
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SMSC USB2601/USB2602

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